1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method for the same. More particularly, the present invention relates to a semiconductor memory device of a full CMOS (Complementary Metal Oxide Semiconductor) type SRAM (Static Random Access Memory) and a manufacturing method for the same.
2. Description of the Related Art
Semiconductor memory devices are mainly classified into a volatile memory in which a stored data is erased while power supply is turned off, and a non-volatile memory in which the stored data is not erased even if the power supply is turned off. RAM is well known as the volatile memory, and ROM (Read Only Memory) is well known as the nonvolatile memory. The RAM is classified into SRAM (Static RAM) and DRAM (Dynamic RAM). Most of these semiconductor memory devices are formed from MOS-type transistors which are excellent in the density.
Also, especially, the SRAM as the volatile memory has an advantage that it is superior in the high-speed operation and does not necessitate a complex refreshing operation indispensable in the DRAM to update memory data periodically. From this reason, SRAM is used in wide fields. The above-mentioned SRAM has one memory cell which stores 1-bit data basically by a flip-flop formed by combining two inverters. There are some types in SRAM according to specific configuration method of the flip-flop.
The most general SRAM at present is a full CMOS type SRAM (hereinafter, to be referred to simply as CMOS type SRAM), in which one memory cell is formed by combining six MOS-type transistors. As shown in an equivalent circuit diagram of FIG. 1, one memory cell MC of the SRAM is composed of six transistors, namely, a pair of NMOS transistors as a pair of access transistors (transfer transistors) Q1 and Q2, a pair of NMOS transistors as a pair of driver transistors (drive transistors) Q3 and Q4, and a pair of PMOS transistors as a pair of load transistors Q5 and Q6. A set of the load transistor Q5 as the PMOS transistor and the driver transistor Q3 as the NMOS transistor and a set of the driver transistor Q4 as the NMOS transistor and the load transistor Q6 as the PMOS transistor form a CMOS-type inverters. The input of each inverter and output of the other inverter are connected so as to cross each other to from a flip-flop.
The gates of the access transistors Q1 and Q2 are both connected with a word line WL and the sources of the transistors Q1 and Q2 are connected with a bit line BL and an inversion bit line BL, respectively. Also, the sources of the load transistors Q5 and Q6 are both connected with a power supply voltage VDD whereas the sources of the driver transistors Q3 and Q4 are both connected with a ground voltage VSS (GND). The above-mentioned memory cells MC are arranged in a matrix to form a memory cell array. In this way, the CMOS type SRAM is manufactured. According to the CMOS type SRAM with the memory cell in which the flip-flop is formed by combining two CMOS-type inverters, the SRAM has the advantage of the CMOS-type inverter, and especially can operate at a low consumption power, in addition to the above-mentioned advantage. Thus, the SRAM is used in the wide fields of the memory.
By the way, in the CMOS type SRAM, an NMOS transistor and a PMOS transistor are formed adjacent to each other on a same semiconductor substrate, as well known. In this case, an NPN-type transistor and a PNP-type transistor are produced parasitically on the sides of the NMOS type transistor and the PMOS type transistor, respectively. For this reason, a phenomenon that extraordinary current flows from the power supply voltage VDD to the ground voltage VSS, i.e., so-called latch-up is caused. In accompaniment with the smaller size of the transistor through the increase of the memory capacity of the SRAM, the latch-up endurance is deteriorated.
As one of the prevention methods of such latch-up, a method is adopted in which the voltages of a P-type well region where NMOS transistors are formed and an N-type well region where a PMOS transistor is formed are fixed. Specifically, the N-type well contact region to be connected with the power supply voltage VDD is formed in the N-type well region whereas the P-type well contact region to be connected with the ground voltage VSS is formed in the P-type well region. In this case, the effect of the latch-up prevention can be improved as much as the N- and P-type well contact regions are frequently arranged to the number of the memory cells. Thus, the latch-up endurance can be improved.
For example, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2001-358232A), in which each of well contact regions is formed to prevent the latch-up. In a memory cell array MCA of the semiconductor memory device, as shown in FIG. 2, a plurality of memory cells MC are arranged in a matrix in a direction of x and a direction of y. An n+-well contact region (high concentration n well contact region) 15a is provided for every 32 memory cells MC arranged in the x direction and an p+-well contact region (high concentration p well contact region) 17a is provided for every 2 memory cells MC arranged in the y direction. In this conventional example, the frequency of the arrangement of the high concentration n-well contact regions 15a in the x direction in this example is one to 32 memory cells MC. On the other hand, the frequency of the arrangement of the high concentration p-well contact region 17a in the y direction is one to the two memory cells MC. It should be noted that a plurality of word lines 23 are arranged in the x direction and inter-word-line regions 91 and 93 are alternately arranged between the word lines 23. A symbol A shows the region of one memory cell MC.
As shown in FIGS. 10 to 13 of Japanese Laid Open Patent Application (JP-P2001-358232A), the high concentration n well contact region 15a is connected with branch sections 33a and 33b as a second layer through plug 61. Also, the high concentration n well contact region 15a is connected with the power supply voltage contact pad layer 49 as a third layer through a plug 75. Also, the high concentration n well contact region 15a is connected with the power supply voltage interconnection 57 as a fourth layer through a plug 81. On the other hand, the high concentration p well contact region 17a is connected with the ground voltage local interconnection 37 as a second layer through a plug 61. Also, the high concentration p well contact region 17a is connected with the ground voltage contact pad layer 47 as a third layer through a plug 75. Moreover, the high concentration p well contact region 17a is connected with the ground voltage interconnection 55 as a fourth layer through a plug 81. By adopting such a structure, the high concentration n well contact region 15a is fixed to the power supply voltage potential whereas the high concentration p well contact region is fixed to the ground voltage. Therefore, the latch up can be prevented.
By the way, in the above conventional semiconductor memory device, it is necessary to add each well contact region for the latch up prevention to the regions for an original memory cell in the memory cell array chip. Therefore, the region of the memory cell array chip increases for the well contact regions, resulting in cost up.
That is, the high concentration n well contact region 15a and the high concentration p well contact region 17a for the latch up prevention which are described in the above conventional example do not have relation to the original operation of the memory cell. Thus, by providing the well contact regions 15a and 17a, the chip area is occupied. As a result, the chip area for the array of the memory cells increases.
For example, as shown in the FIG. 11 of the above conventional example, the high concentration p well contact regions 17a are arranged in the x direction between high concentration n-type source/drain regions 11a2 and 11a3. In order to fix the contact region 17a to the ground voltage, the contact region 17a must be connected with the ground voltage local interconnection 37 as the second layer through the plug 61 as mentioned above. Also, the contact region 17a must be connected with the ground voltage contact pad layer 47 as the third layer through the plug 75 and moreover with the ground voltage interconnection 55 as the fourth layer through a plug 81. In this way, in order to fix the contact regions 17a on the ground voltage, a lot of plugs and interconnection become necessary. However, these plugs and the interconnections are unnecessary components in the original memory cell. They become the cause to increase the chip area of the memory cell array, as mentioned above. That is, if the frequency of the arrangement of the well contact regions 17a and 15a is increased for improving the latch-up endurance, the chip area of the memory cell array increases.
In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-P 2002-343890A). In this conventional example, the semiconductor device has a memory cell which contains a first load transistor, a second load transistor, a first drive transistor, a second drive transistor, a first transfer transistor and a second transfer transistor. The semiconductor device in this conventional example is composed of a first conductive type well region extending in a first direction, a word line extending in the first direction above the first conductive type well region, and a first device forming region provided in the first conductive type well region. The first device forming region contains first to fifth active regions. The third to fifth active regions are provided between the first active region and the second active region. The first active region and the second active region are provided continuously from the third to fifth active regions.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P 2003-60088A). In this conventional example, the semiconductor memory device has a first diffusion region of a P-type formed above a stripe-like N well. A second diffusion region of an N-type is formed above a stripe-like P well which is provided adjacent to the N well. An N well contact region is formed above the N well and the P well as a unit with the second well region. A P well contact region is formed above the N well and the P well as a unit with the first well region.